1. Field of the Invention
The present invention relates to a driving method of plasma display panels, and more particularly, to a plasma display panel driving method in which a reset step, an address step, and a display sustaining step are performed on unit subfields.
2. Background Description
FIG. 1 shows the structure of a general 3-electrode surface-discharge type plasma display panel 1. FIG. 2 shows a display cell of the plasma display panel 1 of FIG. 1. Referring to FIGS. 1 and 2, address electrode lines AR1, AG1 through AGm, and ABm (not shown are the ranges AR1-ARm and AB1 through ABm), front dielectric layer 11 and rear dielectric layer 15, Y electrode lines Y1 through Yn, X electrode lines X1, through Xn, a fluorescent layer 16, barrier ribs 17, and a magnesium monoxide (MgO) layer 12 as a protective membrane are provided between front glass substrate 10 and rear glass substrates 13 of the general surface-discharge type plasma display panel 1.
The address electrode lines AR1, AG1 through AGm, and ABm are disposed on the front surface of the rear glass substrate 13 in a predetermined pattern, and entirely coated with the rear dielectric layer 15. The barrier ribs 17 are formed parallel to the address electrode lines AR1, AG1 through AGm, and ABm on the front surface of the rear dielectric layer 15. The barrier ribs 17 define a discharge area on each display cell and prevents an optical cross-talk between display cells. The fluorescent layer 16 is formed between the barrier ribs 17.
The X electrode lines X1, through Xn and the Y electrode lines Y1 through Yn are formed on the rear surface of the front glass substrate 10 in a predetermined pattern so that they intersect the address electrode lines AR1, AG1 through AGm, and ABm at right angles. Each intersection corresponds to a display cell. To form each of the X electrode lines X1 through Xn, a transparent conductive electrode line Xna of FIG. 2, such as an indium tin oxide (ITO), is combined with a metallic electrode line Xnb of FIG. 2 for increasing conductivity. Likewise, to form each of the Y electrode lines Y1 through Yn, a transparent conductive electrode line Yna of FIG. 2, such as an indium tin oxide (ITO) is combined with a metallic electrode line Ynb of FIG. 2 for increasing conductivity. The X electrode lines X1 through Xn and the Y electrode lines Y1 through Yn are entirely coated with the front dielectric layer 11. The magnesium monoxide (MgO) layer 12, for protecting the panel 1 from a strong electric field, is formed on the entire rear surface of the front dielectric layer 11. Plasma forming gas fills a discharge space 14.
The plasma display panel is driven by sequentially performing a reset step, an address step, and a display sustaining step on unit subfields. In the reset step, the charge states on display cells to be driven are made uniform. In the address step, the charge state of display cells to be turned on is set, and the charge state of display cells to be turned off is also set. In the display sustaining step, the display cells to be turned on perform display discharging.
Here, multiple unit sub-fields operating based on the above-described driving principle are included in a unit frame, so a desired gray scale can be displayed by the display sustaining periods of the respective subfields.
FIG. 3 shows a conventional address-display separation driving method of the Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 3, a unit frame is divided into 8 sub-fields SF1 through SF8 in order to achieve time-division gray scale display. Each of the sub-fields SF1 through SF8 is divided into an address period A1 through A8 and a display sustain period S1 through S8.
In each of the address periods A1 through A8, while a display data signal is applied to the address electrode lines AR1, AG1 through AGm, and ABm of FIG. 1, appropriate scanning pulses are sequentially applied to the Y electrode lines Y1 through Yn. During the application of the scanning pulses, if a high-level display data signal is applied to an address electrode line, wall charges are formed on a discharge cell corresponding to the address electrode line, but the other discharge cells do not gain wall charges.
In each of the display sustain periods S1 through S8, a display discharge pulse is applied to all of the X electrode lines X1 through Xn and all of the Y electrode lines Y1 through Yn in such a way that the display discharge pulse alternates between them. Thus, display discharge occurs on discharge cells having wall charges formed in each of the address periods A1 through A6. Accordingly, the luminance of a plasma display panel is proportional to the length of the display sustain periods S1 through S8 for a unit frame. In the plasma display panel of FIG. 3, the length of the display sustain periods S1 through S8 for a unit frame is 255T (T denotes a unit time). Hence, a unit frame can express 256 gray scales including a zero gray scale, where no display discharge occurs.
A time 1T, corresponding to 20, is set for the display sustain period S1 of the first sub-field SF1. A time 2T, corresponding to 21, is set for the display sustain period S1 of the second sub-field SF2. A time 4T, corresponding to 22, is set for the display sustain period S3 of the third sub-field SF3. A time 8T, corresponding to 23, is set for the display sustain period S4 of the fourth sub-field SF4. A time 16T, corresponding to 24, is set for the display sustain period S5 of the fifth sub-field SF5. A time 32T, corresponding to 25, is set for the display sustain period S6 of the sixth sub-field SF6. A time 64T, corresponding to 26, is set for the display sustain period S7 of the seventh sub-field SF7. A time 128T, corresponding to 27, is set for the display sustain period S8 of the eighth sub-field SF8.
Accordingly, it can be seen from FIG. 3 that when sub-fields to be displayed are appropriately selected from the 8 sub-fields, any of the selected sub-fields can display 256 gray scales including a zero gray scale, in which display discharge does not occur.
In the above-described address-display separation driving method, since the subfields SF1 through SF8 are temporally separated in a unit frame, the address period and the display sustain period are temporally separated in each of the subfields SF1 through SF8. More specifically, in an address period, each pair of X and Y electrodes is addressed, and waits for the next operation until the other pairs of X and Y electrodes are all addressed. Consequently, the time for the address period in each subfield is lengthened, while the display sustain period is relatively shortened. This lowers the luminance of light emitted from a plasma display panel adopting the above method. In order to solve this problem, an address-while-display driving method as shown in FIG. 4 have been developed.
FIG. 4 shows a conventional address-while-display driving method of the Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 4, a unit frame is divided into 8 subfields SF1 through SF8 in order to achieve time-division gray-scale display. Here, the subfields overlap with one another with respect to the Y electrode lines Y1 through Yn to constitute a unit frame. Hence, all of the subfields SF1 through SF8 exist at every time point and an addressing time slot is set between display discharge pulses in order to perform each addressing.
A reset step, an address step, and a display sustaining step are performed on each of the subfields, and the time allocated to each of the subfields is determined based on a display discharging time corresponding to a gray scale. If 8-bit image data displays 256 gray scales per unit frame and the unit frame (generally, 1/60 sec) is divided into 255 unit periods, the first subfield SF1, driven based on the least significant bit (LSB) image data, has one (20) unit period. The second subfield SF2 has 2 (21) unit periods, the third subfield SF3 has 4 (22) unit periods, the fourth subfield SF4 has 8 (23) unit periods, the fifth subfield SF5 has 16 (24) unit periods, the sixth subfield SF6 has 32 (25) unit periods, the seventh subfield SF7 has 64 (26) unit periods, and the eighth subfield SF8, driven based on the most significant bit (MSB) image data, has 128 (27) unit periods.
Since the sum of the unit periods allocated to the subfields is 255 unit periods, 255 gray scales can be displayed. If a gray scale in which display discharge does not occur on any subfield is included, 256 gray scales can be displayed.
FIG. 5 shows a general driving apparatus for the plasma display panel of FIG. 1. Referring to FIG. 5, the general driving apparatus for the plasma display panel 1 of FIG. 1 includes an image processor 66, a logic controller 62, an address driver 63, an X-driver 64, and a Y-driver 65. The image processor 66 converts an external analog image signal into a digital signal and generates an internal image signal, for example, 8-bit red (R) image data, 8-bit green (G) image data, 8-bit blue (B) image data, a clock signal, and vertical and horizontal synchronous signals. The logic controller 62 generates driving control signals SA, SY, and SX according to the internal image signal received from the image processor 66. The address driver 63 processes the address signal SA out of the driving control signals SA, SY, and SX to obtain a display data signal, and applies the display data signal to address electrode lines. The X-driver 64 processes the X driving control signal SX out of the driving control signals SA, SY, and SX and applies the resultant signal to X electrode lines. The Y-driver 65 processes the Y driving control signal SY out of the driving control signals SA, SY, and SX and applies the resultant signal to Y electrode lines.
FIG. 6 shows driving signals applied to a unit subfield on the panel of FIG. 1 by the address-display separation driving method of FIG. 3. Referring to FIG. 6, reference character SAR1 . . . ABm denotes a driving signal applied to the address-electrode lines AR1, AG1 through AGm, and ABm of FIG. 1, reference character SX1 . . . Xn denotes a driving signal applied to the X electrode lines X1 through Xn of FIG. 1, and reference characters SY1 through SYn denote a driving signal applied to the Y electrode lines Y1 through Yn of FIG. 1, respectively. FIG. 7 shows wall charges distributed on a display cell at the point in time immediately after a gradual rising voltage is applied to the Y electrode lines Y1 through Yn during a reset period PR of FIG. 6. FIG. 8 shows wall charges distributed on a display cell at the point in time when the reset period PR of FIG. 6 terminates.
Referring to FIG. 6, during the reset period PR of a unit subfield SF, first, the voltage applied to the X electrode lines X1 through Xn continuously increases from a ground voltage VG to a second voltage VS, for example, 155 V. At this time, the ground voltage VG is applied to the Y electrode lines Y1 through Yn and the address electrode lines AR1, AG1 through AGm, and ABm. Accordingly, while weak discharge occurs between the X electrode lines X1, through Xn and the Y electrode lines Y1 through Yn and between the X electrode lines X1 through Xn and the address electrode lines AR1 through ARm, AG1 through AGm and AB1 through ABM, negative wall charges are formed around the X electrode lines X1 through Xn.
Next, the voltage applied to the Y electrode lines Y1 through Yn continuously increases from the second voltage VS, for example, 155 V, to the highest voltage (VSET+VS), for example, 355 V. The voltage (VSET+VS) is obtained by adding a third voltage VSET to the second voltage VS. While the voltages SY1 through SYn increase from the second voltage to the highest voltage, the ground voltage VG is applied to the X electrode lines X1 through Xn and the address electrode lines AR1 through ABm. Accordingly, weak discharge occurs between the X electrode lines X1 through Xn and the Y electrode lines Y1 through Yn, while weaker discharge occurs between the Y electrode lines Y1 through Yn and the address electrode lines AR1, AG1 through AGm, and ABm. The reason why the discharge between the X electrode lines X1 through Xn and the Y electrode lines Y1 through Yn is stronger than the discharge between the Y electrode lines Y1 through Yn and the address electrode lines AR1, AG1 through AGm, and ABm is that negative wall charges have been formed around the X electrode lines X1 through Xn. Consequently, many negative wall charges are formed around the Y electrode lines Y1 through Yn, positive wall charges are formed around the X electrode lines X1 through Xn, and a few positive wall charges are formed around the address electrode lines AR1, AG1 through AGm, and ABm, as illustratively shown in FIG. 7.
Thereafter, while the voltage applied to the X electrode lines X1 through Xn is maintained at the second voltage VS, the voltage applied to the Y electrode lines Y1 through Yn continuously decreases from the second voltage VS to the ground voltage VG. At this time, the ground voltage VG is applied to the address electrode lines AR1, AG1 through AGm, and ABm. Consequently, due to weak discharge occurring between the X electrode lines X1 through Xn and the Y electrode lines Y1 through Yn, some of the negative wall charges around the Y electrode lines Y1 through Yn move toward the X electrode lines X1 through Xn, as illustratively shown in FIG. 8. Also, due to the ground voltage VG applied to the address electrode lines AR1, AG1 through AGm, and ABm, the number of positive wall charges around the address electrode lines AR1, AG1 through AGm, and ABm slightly increases.
Subsequently, during the subsequent address period PA, smooth addressing can be performed accordingly as a display data signal is applied to the address electrode lines AR1, AG1 through AGm, and ABm. The Y electrode lines Y1 through Yn, biased to a fourth voltage VSCAN, which is lower than the second voltage VS, are sequentially subject to a scanning signal with the ground voltage VG. If a display cell is selected, a display data signal with positive address voltage VA is applied to a corresponding address electrode line. Otherwise, a display data signal with the ground voltage VG is applied to a corresponding address electrode line. Accordingly, when a display data signal with the positive address voltage VA is applied while a scanning pulse with the ground voltage VG is applied, a display cell corresponding to this case has wall charges formed on a corresponding display cell due to address discharge. Otherwise, a display cell corresponding to this case does not have wall charges. At this time, in order to achieve more accurate and efficient address discharge, the second voltage VS is applied to the X electrode lines X1 through Xn.
Subsequently, during the display sustaining period PS, a display sustaining pulse with the second voltage VS is applied to each of the X electrode lines X1 through Xn and each of the Y electrode lines Y1 through Yn in such a way that the display sustaining pulse alternates between them. As a result, discharge for sustaining display occurs on display cells having wall charges formed during the address period PA.
In FIG. 9A, reference character SY1 . . . Yn denotes a driving signal applied to all of the Y electrode lines Y1 through Yn, and reference character SX1 . . . Xn denotes a driving signal applied to all of the X electrode lines X1 through Xn. Referring to FIG. 9A, the widths of conventional alternating current (AC) pulses and pulse periods applied during the display sustaining period are uniform. Accordingly, during the display sustaining period, an AC pulse of a single period (T1), that is, a single frequency (1/T1), is applied.
As shown illustratively in FIG. 9B, in a conventional driving method as described above, the maximum electric field intensity EOLD for a particular frequency f1 increases, which increases the influence of electromagnetic interference (EMI).
It is an object of the present invention to provide a driving method of a plasma display panel, by which electromagnetic interference is reduced.
To achieve the above object, the present invention provides a plasma display panel driving method in which a reset step, an address step, and a display sustaining step are performed on unit subfields. In the reset step, the charge states of display cells to be driven are uniform. In the address step, wall charges with a predetermined voltage are formed on only display cells to be turned on. In the display sustaining step, alternating current pulses are applied to all of the display cells, so that only the display cells having the wall charges perform display discharge. The width of AC pulses applied to all of the display cells varies in the display sustain step.
In the driving method according to the present invention, the width of AC pulses applied to all of the display cells varies in the display sustaining step so that the electric field due to the AC pulses is dispersed with respect to a plurality of frequencies. In this way, electromagnetic interference is reduced.